The present disclosure relates to interconnect level structures and particularly to size-filtered multimetal structures in which metal lines having different widths have different metallic compositions, an electrically programmable fuse (eFuse) employing a different material for a metallic fuselink than for a metallic anode and a metallic cathode, and methods of manufacturing the same.
Interconnect level structures, which are also referred to as back-end-of-line (BEOL) interconnect structures, are employed in semiconductor chips to provide horizontal and vertical electrical connections among various semiconductor devices and/or between semiconductor devices and input/output pads that are connected to pins on a packaging substrate. Metal lines provide horizontal electrical connection, and metal vias provide vertical interconnection. Metal lines and metal vias are embedded in dielectric layers, which are located on a semiconductor substrate on which various semiconductor devices are formed.
Various types of additional metal structures can be formed in the dielectric layers. Such additional metal structures include, but are not limited to, capacitors, inductors, resistors, and electrical fuses. An electrical fuse formed as a metal interconnect structure, which is herein referred to as a metallic electrical fuse, requires much less device area than a metal-silicide-based electrically programmable fuse.
Different metal structures in dielectric layers and/or different components of a metal structure may require different properties for optimal performance. For example, a metallic electrical fuse requires an anode structure and a cathode structure that are resistant to electromigration and an electromigratable fuselink. Thus, integration of various metallic device components within the same level of metal interconnect structure may require compromise among various device performance requirements.